Invention Grant
- Patent Title: Memory interface mapping
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Application No.: US17668571Application Date: 2022-02-10
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Publication No.: US12057192B2Publication Date: 2024-08-06
- Inventor: Sreeja Menon , Charles J. Wilson , Sudhir Kumar Katla Shetty , Larry Arbuthnot , Nikhil Raghavendra Rao
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Holland & Knight LLP
- Agent Mark H. Whittenberger
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C7/10 ; G11C8/18 ; G11C29/42

Abstract:
System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin adjustments, correctly calculate error detection coding, and correctly read vendor identification information.
Public/Granted literature
- US20220262415A1 MEMORY INTERFACE MAPPING Public/Granted day:2022-08-18
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