Invention Grant
- Patent Title: In-line electrical detection of defects at wafer level
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Application No.: US17851261Application Date: 2022-06-28
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Publication No.: US12061229B2Publication Date: 2024-08-13
- Inventor: Yu-Hsuan Huang , Chien-Liang Chen , Pei-Hsuan Lee
- Applicant: Taiwan Semiconductor Manufacturing Company
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Lippes Mathias LLP
- Main IPC: G01R31/307
- IPC: G01R31/307 ; H01L21/66

Abstract:
In a semiconductor manufacturing method includes providing a plurality of patterns on a semiconductor substrate. The patterns include an NMOS structure arranged next to an N+/N well structure, and/or a PMOS structure arranged next to a P+/P well structure. The method further includes: receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.
Public/Granted literature
- US20230417830A1 IN-LINE ELECTRICAL DETECTION OF DEFECTS AT WAFER LEVEL Public/Granted day:2023-12-28
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