Invention Grant
- Patent Title: Inverse element arithmetic apparatus and memory system
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Application No.: US17197256Application Date: 2021-03-10
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Publication No.: US12061665B2Publication Date: 2024-08-13
- Inventor: Hajime Matsui
- Applicant: Kioxia Corporation
- Applicant Address: JP Tokyo
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP 20153341 2020.09.11
- Main IPC: G06F17/16
- IPC: G06F17/16 ; G06F7/50 ; G06F21/64 ; G06F21/78 ; G06F21/79 ; H04L9/32

Abstract:
According to one embodiment, in an inverse element arithmetic apparatus, a word unit processing unit, as approximate calculation loop for extended binary GCD process, iterates a first loop in a case where a value of |r−s| is a subtraction threshold or more, and is capable of iterating a second loop instead of the first loop in a case where the value of |r−s| is smaller than the subtraction threshold. In the first loop, values of r, s, a, b, m, and n is updated and an update matrix M is generated or updated. In the second loop, the values of m and n are updated without updating the values of r, s, a, b and the update matrix M. The control unit terminates the loop of the inverse element arithmetic process in a case where a loop number of times of the inverse element arithmetic process reaches a number-of-times threshold.
Public/Granted literature
- US20220083624A1 INVERSE ELEMENT ARITHMETIC APPARATUS AND MEMORY SYSTEM Public/Granted day:2022-03-17
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