Invention Grant
- Patent Title: Semiconductor device including combination rows and method and system for generating layout diagram of same
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Application No.: US17023286Application Date: 2020-09-16
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Publication No.: US12061856B2Publication Date: 2024-08-13
- Inventor: Shih-Wei Peng , Jiann-Tyng Tzeng
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- Main IPC: G06F30/392
- IPC: G06F30/392 ; H01L23/522 ; H01L23/528 ; H01L27/02 ; H01L27/092

Abstract:
A method generating a layout diagram includes: arranging the layout diagram into rows; configuring one or more of the rows as combination rows, the combination-row-configuring including relative to a second direction substantially perpendicular to the first direction, setting a height of each of the one or more combination rows to be substantially equal to a sum of a first height of a first cell and a second height of a second cell, the first cell being different than the second cell, and the first height being different than the second height; and populating each of the one or more combination rows including: stacking a first instance of the first cell on a first instance of the second cell, or stacking a second instance of the second cell on a second instance of the first cell.
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