A memory device includes: a refresh control circuit configured to generate a self-refresh command and a refresh address, word line control circuits configured to control a refresh operation of a plurality of word lines, a group management circuit configured to classify N address groups by grouping the refresh addresses to be generated by the refresh control circuit and to select from the N address groups, a current address group including a refresh address to be currently generated and a subsequent address group including a refresh address to be generated after the current address group according to the predetermined order, a row control circuit configured to group the plurality of word line control circuits with N control signals respectively corresponding to the N address groups, respectively, and a supply control circuit configured to activate signals corresponding to the current and subsequent address groups among the N control signals.