Invention Grant
- Patent Title: Page buffer comprising a bit line controller and latch units
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Application No.: US17487705Application Date: 2021-09-28
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Publication No.: US12062403B2Publication Date: 2024-08-13
- Inventor: Soo Yeol Chai , Jong Woo Kim
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si
- Agency: WILLIAM PARK & ASSOCIATES LTD.
- Priority: KR 20210045960 2021.04.08
- Main IPC: G11C16/26
- IPC: G11C16/26 ; G11C7/10 ; G11C16/10 ; G11C16/24 ; G11C16/34

Abstract:
A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.
Public/Granted literature
- US20220328114A1 PAGE BUFFER, SEMICONDUCTOR MEMORY HAVING THE SAME, AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY Public/Granted day:2022-10-13
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