Invention Grant
- Patent Title: Method for forming an integrated circuit having transistor gates over an interconnection structure
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Application No.: US17385634Application Date: 2021-07-26
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Publication No.: US12062658B2Publication Date: 2024-08-13
- Inventor: Yu-Lien Huang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/768 ; H01L21/8234 ; H01L23/485 ; H01L23/528 ; H01L27/06 ; H01L27/088 ; H01L29/08 ; H01L29/78

Abstract:
An integrated circuit structure includes a lower interconnect structure, a first semiconductor fin, a lower gate structure, first source/drain structures, an upper gate structure, and an upper interconnect structure. The first semiconductor fin is above the lower interconnect structure. The lower gate structure is under the first semiconductor fin and extends across the first semiconductor fin. The first source/drain structures are in the first semiconductor fin and on opposite sides of the lower gate structure. The first source/drain structures forms a lower transistor with the lower gate structure. The upper gate structure is above the first semiconductor fin and extends across the first semiconductor fin. The upper gate structure forms an upper transistor with the first source/drain structures. The upper interconnect structure is above the upper gate.
Public/Granted literature
- US20220320084A1 INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2022-10-06
Information query
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