Invention Grant
- Patent Title: Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well
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Application No.: US17808647Application Date: 2022-06-24
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Publication No.: US12068308B2Publication Date: 2024-08-20
- Inventor: Robert J. Gauthier, Jr. , Alain F. Loiseau , Souvick Mitra , Tsung-Che Tsai , Meng Miao , You Li
- Applicant: GlobalFoundries U.S. Inc.
- Applicant Address: US NY Malta
- Assignee: GlobalFoundries U.S. Inc.
- Current Assignee: GlobalFoundries U.S. Inc.
- Current Assignee Address: US NY Malta
- Agency: Hoffman Warnick LLC
- Agent Anthony Canale
- The original application number of the division: US16983071 2020.08.03
- Main IPC: H01L27/02
- IPC: H01L27/02

Abstract:
Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.
Public/Granted literature
- US20220320073A1 INTEGRATED CIRCUIT STRUCTURE WITH AVALANCHE JUNCTION TO DOPED SEMICONDUCTOR OVER SEMICONDUCTOR WELL Public/Granted day:2022-10-06
Information query
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