Invention Grant
- Patent Title: High capacity memory circuit with low effective latency
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Application No.: US18306073Application Date: 2023-04-24
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Publication No.: US12073082B2Publication Date: 2024-08-27
- Inventor: Youn Cheul Kim , Richard S. Chernicoff , Khandker Nazrul Quader , Robert D. Norman , Tianhong Yan , Sayeef Salahuddin , Eli Harari
- Applicant: SUNRISE MEMORY CORPORATION
- Applicant Address: US CA San Jose
- Assignee: SUNRISE MEMORY CORPORATION
- Current Assignee: SUNRISE MEMORY CORPORATION
- Current Assignee Address: US CA San Jose
- Agency: VLP Law Group LLP
- Agent Edward C. Kwok
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G06F3/06 ; H01L23/00 ; H01L25/18

Abstract:
A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.
Public/Granted literature
- US20230259283A1 HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCY Public/Granted day:2023-08-17
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