A memory controller issues a command to a semiconductor memory device in response to an access request from an arithmetic unit to the semiconductor memory device having multiple ranks. The memory controller includes an access request holder, an access request selector, a command generator, a refresh interval counter and a refresh counter. The access request selector calculates a total processing period for each of the ranks, selects multiple access requests as an access request group sent to an access target rank, and determines a processing order of the access requests in the selected access request group. The command generator issues an access command to the access target rank in order, and issues a refresh command to a refresh target rank.