Invention Grant
- Patent Title: Circuit assembly
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Application No.: US17830191Application Date: 2022-06-01
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Publication No.: US12074103B2Publication Date: 2024-08-27
- Inventor: Wenliang Chen , Jun Gu , Masaru Haraguchi , Takashi Kubo , Chien-An Yu , Chun Yi Lin
- Applicant: AP Memory Technology Corp.
- Applicant Address: TW Zhubei
- Assignee: AP Memory Technology Corp.
- Current Assignee: AP Memory Technology Corp.
- Current Assignee Address: TW Zhubei
- Agency: Chen Yoshimura LLP
- The original application number of the division: US17010517 2020.09.02
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/48 ; H01L23/532 ; H10B12/00 ; H01L23/40

Abstract:
A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.
Public/Granted literature
- US20220302021A1 CIRCUIT ASSEMBLY Public/Granted day:2022-09-22
Information query
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