Invention Grant
- Patent Title: Chip package structure
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Application No.: US18319610Application Date: 2023-05-18
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Publication No.: US12074119B2Publication Date: 2024-08-27
- Inventor: Jiun-Ting Chen , Ying-Ching Shih , Szu-Wei Lu , Chih-Wei Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- The original application number of the division: US16395385 2019.04.26
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/56 ; H01L23/31 ; H01L25/00 ; H01L25/065

Abstract:
A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar between the first chip structure and the second chip structure. In addition, the chip package structure includes an underfill layer between the first chip structure and the second chip structure and between the anti-warpage bar and the substrate. A topmost surface of the underfill layer is lower than a top surface of the anti-warpage bar.
Public/Granted literature
- US20230307381A1 CHIP PACKAGE STRUCTURE Public/Granted day:2023-09-28
Information query
IPC分类: