Invention Grant
- Patent Title: Gate structure and method
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Application No.: US18340758Application Date: 2023-06-23
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Publication No.: US12074207B2Publication Date: 2024-08-27
- Inventor: Chung-Liang Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Seed IP Law Group LLP
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L21/8238 ; H01L27/092 ; H01L29/06 ; H01L29/40 ; H01L29/423 ; H01L29/51 ; H01L29/66 ; H01L29/786

Abstract:
A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.
Public/Granted literature
- US20230343847A1 GATE STRUCTURE AND METHOD Public/Granted day:2023-10-26
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