A method of passively braking a motor to reduce a current motor speed includes generating at least one control signal to control a first load current generated by a first half bridge circuit and a second load current generated by a second half bridge circuit. During passive braking, the method includes synchronously driving a first high-side transistor and a second high-side transistor between their respective switching states at an alternating shorting frequency such that they are simultaneously in a same switching state, and synchronously driving a first low-side transistor and a second low-side transistor between their respective switching states at the alternating shorting frequency such that they are simultaneously in a same switching state, wherein the first high-side transistor and the second high-side transistor are driven in a complementary manner to the first low-side transistor and the second low-side transistor according to a predetermined duty cycle.