A memory device includes a first SRAM cell, a second SRAM cell, a first inter transistor and a second inter transistor. The first SRAM cell includes two first pull-up transistors, two first pull-down transistors, and two first pass-gate transistors. The second SRAM cell includes two second pull-up transistors, two second pull-down transistors, and two second pass-gate transistors. The first inter transistor and the second inter transistor are electrically connected to the first SRAM cell and the second SRAM cell.