Invention Grant
- Patent Title: Method of forming a stacked memory structure with insulating patterns
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Application No.: US18186062Application Date: 2023-03-17
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Publication No.: US12075623B2Publication Date: 2024-08-27
- Inventor: Changhan Kim , In Ku Kang , Sun Young Kim
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si
- Agency: William Park & Associates Ltd.
- Priority: KR 20200021284 2020.02.20
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H01L21/28 ; H01L29/423 ; H10B41/27 ; H10B41/35 ; H10B43/35 ; H10B63/00 ; H10N70/00 ; H10N70/20

Abstract:
A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.
Public/Granted literature
- US12048160B2 Method of forming a stacked memory structure with insulating patterns Public/Granted day:2024-07-23
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