Methods and structures are described for detecting clock anomalies, including anomalies in which the clock oscillates at a faster than expected rate or exhibits a shorter than expected clock phase instance. Example methods include starting a timer responsive to the start of a clock phase, wherein the timer duration is shorter than an expected duration of the clock phase. If the clock phase ends before the timer expires, a fast clock detection signal is asserted. Example structures include fast clock detection logic coupled to a clock signal. The logic includes a timer, circuitry to start the timer responsive to the clock signal entering a monitored phase, and error detection circuitry to assert a fast clock detection output if the monitored phase ends before the timer expires. In some embodiments, the timer duration may be based on a measured duration of a previous clock phase.