A chip-to-chip process variation aware power efficiency optimization method that includes determining, using an adaptive voltage scaling (AVS) module of a processing unit in a system, an optimal voltage identification (VID) based on chip process variation. The method outputs the optimal VID from the AVS module to a voltage regulator of the system. The method adjusts a direct current (DC) load line setting based on the optimal VID of the processing unit in the system. The method regulates, using the voltage regulator of the system, a voltage supplied to the processing unit based on the DC load line setting.