Invention Grant
- Patent Title: Method and apparatus for efficient chip-to-chip data transfer
-
Application No.: US18101806Application Date: 2023-01-26
-
Publication No.: US12079132B2Publication Date: 2024-09-03
- Inventor: Jamshed Jalal , Ashok Kumar Tummala , Wenxuan Zhang , Daniel Thomas Pinero , Tushar P Ringe
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Leveque Intellectual Property Law, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0888

Abstract:
Data transfer between caching domains of a data processing system is achieved by a local coherency node (LCN) of a first caching domain receiving a read request for data associated with a second caching domain, from a requesting node of the first caching domain. The LCN requests the data from the second caching domain via a transfer agent. In response to receiving a cache line containing the data from the second caching domain, the transfer agent sends the cache line to the requesting node, bypassing the LCN and, optionally, sends a read-receipt indicating the state of the cache line to the LCN. The LCN updates a coherency state for the cache line in response to receiving the read-receipt from the transfer agent and a completion acknowledgement from the requesting node. Optionally, the transfer agent may send the cache line via the LCN when congestion is detected in a response channel of the data processing system.
Public/Granted literature
- US20240256460A1 Method and Apparatus for Efficient Chip-To-Chip Data Transfer Public/Granted day:2024-08-01
Information query