Memory cache-line bounce reduction for pointer ring structures
Abstract:
A system includes a memory including a ring buffer having a plurality of slots and at least one processor in communication with the memory. A subset of the plurality of slots are initialized with an initialization value. Additionally, the at least one processor includes a consumer processor and a producer processor. The producer processor is configured to receive a memory entry, identify an available slot in the ring buffer for the memory entry, and store the memory entry in the available slot at an offset in the ring buffer. The initialization value is interpreted as an unavailable slot by the producer processor. The consumer processor is configured to consume the memory entry and invalidate one of the subset of slots in the ring buffer by overwriting the initialization value with an invalid value to transition the one of the subset of slots from an unavailable slot to an available slot.
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