Invention Grant
- Patent Title: Efficient address translation
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Application No.: US17892879Application Date: 2022-08-22
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Publication No.: US12079138B2Publication Date: 2024-09-03
- Inventor: Jianhui Li , Yong Wu , Yihua Jin , Xueliang Zhong , Xiao Lin
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: HANLEY, FLIGHT & ZIMMERMAN, LLC
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F9/30 ; G06F9/355 ; G06F9/455

Abstract:
An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.
Public/Granted literature
- US20220405210A1 EFFICIENT ADDRESS TRANSLATION Public/Granted day:2022-12-22
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