A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.