Provided is a synchronous FIFO, including a data storage circuit, a first logic circuit, a second logic circuit and indication circuits. The data storage circuit includes N first registers, N first multiplexers and N first deciders, where N is a positive integer; and the N first registers and the N first multiplexers are alternately connected. Based on the registers, the synchronous FIFO builds a storage required by the FIFO, and primarily includes the registers, the multiplexers and the deciders, the use of an RAM is avoided, that is, there is no need to occupy the RAM, and there is no need to perform RAM read-write enabling and address control, thereby avoiding wasting RAM resources. In designs with lower storage depth requirements, few resources are occupied, so that a chip area is greatly reduced, the cost is reduced, and layout and wiring are more convenient.