Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.