A memory device is provided. The memory device comprises a memory cell array, a first control circuit, and a second control circuit. The memory cell array has a plurality of memory cells, wherein each of the plurality of memory cells comprises a first port and a second port. The first control circuit is disposed on a first side of the memory cell array and is arranged to electrically connect to the plurality of first ports. The second control circuit is disposed on the first side of the memory cell array and is arranged to electrically connect to the plurality of second ports. The plurality of first ports are different from the plurality of second ports.