According to one embodiment, a device includes a memory cell array that includes a plurality of memory cells connected to a plurality of pieces of gate wiring, and a test control circuit that includes a plurality of control units connected to the plurality of pieces of gate wiring. The control units each includes a transistor that includes a gate connected to a first node, one end connected to the corresponding gate wiring and another end connected to a second node, and a load unit connected between the first node and the second node. When the gate wiring is being discharged, the transistor is turned on. The gate wiring is connected to the second node via the transistor in an on state. After the gate wiring is discharged, the load unit discharges the first node.