Invention Grant
- Patent Title: Semiconductor device and method to minimize stress on stack via
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Application No.: US17010610Application Date: 2020-09-02
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Publication No.: US12080600B2Publication Date: 2024-09-03
- Inventor: Yaojian Lin , Seng Guan Chow
- Applicant: STATS ChipPAC Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: PATENT LAW GROUP: Atkins and Association, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L21/66 ; H01L21/78 ; H01L23/498 ; H01L23/31 ; H01L23/538

Abstract:
A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.
Information query
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