Invention Grant
- Patent Title: Die embedded in substrate with stress buffer
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Application No.: US18168319Application Date: 2023-02-13
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Publication No.: US12080657B2Publication Date: 2024-09-03
- Inventor: Jefferson Sismundo Talledo
- Applicant: STMicroelectronics, Inc.
- Applicant Address: PH Calamba
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: PH Calamba
- Agency: Seed IP Law Group LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L21/683 ; H01L23/00

Abstract:
The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.
Public/Granted literature
- US20230187384A1 DIE EMBEDDED IN SUBSTRATE WITH STRESS BUFFER Public/Granted day:2023-06-15
Information query
IPC分类: