Invention Grant
- Patent Title: Semiconductor package including a molding layer
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Application No.: US17646672Application Date: 2021-12-30
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Publication No.: US12080676B2Publication Date: 2024-09-03
- Inventor: Hae-Jung Yu
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: F. Chau & Associates, LLC
- Priority: KR 20210046425 2021.04.09
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/00 ; H01L23/48 ; H01L23/498 ; H01L25/065

Abstract:
A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.
Public/Granted literature
- US20220328445A1 SEMICONDUCTOR PACKAGE INCLUDING A MOLDING LAYER Public/Granted day:2022-10-13
Information query
IPC分类: