Invention Grant
- Patent Title: Dual inner spacer epitaxy in monolithic stacked FETs
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Application No.: US17655595Application Date: 2022-03-21
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Publication No.: US12080709B2Publication Date: 2024-09-03
- Inventor: Sagarika Mukesh , Julien Frougier , Nicolas Jean Loubet , Ruilong Xie
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent David K. Mattheis
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L21/822 ; H01L27/12 ; H01L29/786

Abstract:
A semiconductor device includes a bottom device, a top device, and a spacer. The bottom device includes a first set of silicon sheets and a first source-drain epitaxy in direct contact with the first set of silicon sheets. The top device includes a second set of silicon sheets, a set of separation layers, and a second source-drain epitaxy. Each silicon sheet of the second set of silicon sheets is separated by a separation layer of the set of separation layers. The second source-drain epitaxy is arranged in direct contact with the second set of silicon sheets. The spacer is arranged between the first source-drain epitaxy and the second source-drain epitaxy and is arranged between each silicon sheet of the second set of silicon sheets.
Public/Granted literature
- US20230299080A1 DUAL INNER SPACER EPITAXY IN MONOLITHIC STACKED FETS Public/Granted day:2023-09-21
Information query
IPC分类: