Invention Grant
- Patent Title: Hybrid shielding sockets with impedance tuning for integrated circuit device test tooling
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Application No.: US17500937Application Date: 2021-10-13
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Publication No.: US12085587B2Publication Date: 2024-09-10
- Inventor: Nasser Barabi , Chee Wah Ho , Hin Lum Lee
- Applicant: ESSAI, INC.
- Applicant Address: US CA Fremont
- Assignee: ESSAI, INC.
- Current Assignee: ESSAI, INC.
- Current Assignee Address: US CA Fremont
- Main IPC: G01R1/067
- IPC: G01R1/067
Abstract:
High frequency operation of an integrated circuit test system is greatly extended by incorporation of a dedicated high frequency signal element that provides a circuit specific compensation network as part of the intermediation circuit board that enables connectivity between test equipment and the integrated circuit under test.
Public/Granted literature
- US20220236302A1 HYBRID SHIELDING SOCKETS WITH IMPEDANCE TUNING FOR INTEGRATED CIRCUIT DEVICE TEST TOOLING Public/Granted day:2022-07-28
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