Invention Grant
- Patent Title: Random sparsity handling in a systolic array
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Application No.: US17211627Application Date: 2021-03-24
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Publication No.: US12086205B2Publication Date: 2024-09-10
- Inventor: Chunhui Mei , Hong Jiang , Jiasheng Chen , Yongsheng Liu , Yan Li
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06F17/16
- IPC: G06F17/16 ; G06F7/544 ; G06F9/30 ; G06F15/80 ; G06F17/11

Abstract:
Matrix multiply units can take advantage of input sparsity by zero gating ALUs, which saves power consumption, but compute throughput does not increase. To improve compute throughput from sparsity, processing resources in a matrix accelerator can skip computation with zero involved in input or output. If zeros in input can be skipped, the processing units can focus calculations on generating meaningful non-zero output.
Public/Granted literature
- US20220309124A1 RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY Public/Granted day:2022-09-29
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