Invention Grant
- Patent Title: High throughput parallel architecture for recursive sinusoid synthesizer
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Application No.: US18134737Application Date: 2023-04-14
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Publication No.: US12086568B2Publication Date: 2024-09-10
- Inventor: Ankur Bal , Rupesh Singh
- Applicant: STMicroelectronics International N.V.
- Applicant Address: CH Geneva
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: CH Geneva
- Agency: Crowe & Dunlevy LLC
- The original application number of the division: US16988912 2020.08.10
- Main IPC: G06F7/544
- IPC: G06F7/544 ; G06F7/548 ; H03K3/037 ; H03K5/01 ; H03K5/00

Abstract:
A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
Public/Granted literature
- US20230251829A1 HIGH THROUGHPUT PARALLEL ARCHITECTURE FOR RECURSIVE SINUSOID SYNTHESIZER Public/Granted day:2023-08-10
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