In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command, control the page buffer circuit to store suspended program information associated with a suspension of the program operation, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by the suspension of the program operation through a storage of a piece of program information from the suspended program information in a memory controller, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.