A storage system includes a memory controller providing a clock signal; a buffer having a first duty cycle corrector to receive the clock signal and a chip selection signal from the memory controller, perform a first duty correction operation on the clock signal using a first data code and output a first corrected clock signal, a register to store the first data code regarding the chip selection signal, and a sampler to receive a data signal and a data strobe signal regarding the data signal and output a data stream; and a nonvolatile memory having a second duty cycle corrector to receive the first corrected clock signal from the buffer and perform a second duty correction operation on the first corrected clock signal using a second data code and out a second corrected clock signal, a second data code generation circuit to generate the second data code based on the second corrected clock signal, and a data strobe signal generator to generate the data strobe signal based on the second corrected clock signal and provide the data strobe signal to the buffer.