Invention Grant
- Patent Title: High aspect ratio via fill process employing selective metal deposition and structures formed by the same
-
Application No.: US17566262Application Date: 2021-12-30
-
Publication No.: US12087628B2Publication Date: 2024-09-10
- Inventor: Rahul Sharangpani , Raghuveer S. Makala , Fumitaka Amano
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: THE MARBURY LAW GROUP PLLC
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532 ; H01L23/535

Abstract:
A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second metallic material portion including a second metal. A metal-semiconductor alloy portion including a first metal-semiconductor alloy of the first metal and a semiconductor material is located underneath the second metallic material portion, and contacts a top surface of the first metal interconnect structure.
Public/Granted literature
Information query
IPC分类: