- Patent Title: High performance 3D vertical transistor device enhancement design
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Application No.: US17490182Application Date: 2021-09-30
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Publication No.: US12087817B2Publication Date: 2024-09-10
- Inventor: Mark I. Gardner , H. Jim Fulford
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/10

Abstract:
A microfabricated transistor device includes a vertical stack of two or more channels of field effect transistors on a semiconductor substrate. Each of the channels has a vertical conductive path relative to a surface of the semiconductor substrate. At least one of the channels includes a shell formed around a core material, the shell including epitaxial material. The vertical stack can include a channel for a PMOS field effect transistor, and a channel for an NMOS field effect transistor.
Public/Granted literature
- US20220238652A1 HIGH PERFORMANCE 3D VERTICAL TRANSISTOR DEVICE ENHANCEMENT DESIGN Public/Granted day:2022-07-28
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