A video processing circuit has a bus interface circuit configured to communicatively couple the video processing circuit to an imaging device over a multidrop differential serial link; detector circuits configured to detect sequentially occurring signaling states of the multidrop differential serial link, the sequentially occurring signaling states preceding a transition of the bus interface circuit from a low-power mode to a high-speed mode; and a controller configured to: cause the bus interface circuit to receive data transmitted over the multidrop differential serial link in the high-speed mode when a duration of each signaling state in the sequentially occurring signaling states exceeds a minimum duration defined for the each signaling state; and cause the bus interface circuit to return to the low-power mode when one signaling state of the sequentially occurring signaling states does not exceed a corresponding minimum duration defined for the one signaling state.