A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array through word lines and bit lines, and suitable for performing one or more program loops on memory cells that are coupled to a selected word line of the word lines, each program loop including a program voltage application operation and a program verification operation; and a program control circuit suitable for controlling the peripheral circuit to decrease a level of a precharge voltage that is applied to the bit lines during the program verification operation when the number of program loops that are performed is greater than a reference number.