The present disclosure relates to systems and methods for video decoding with a video decoding chip. The video decoding chip may include one or more input channels and one or more output channels. The systems and methods may include detecting a flag bit of each of the one or more input channels. The flag bit of an input channel may indicate a status of receiving its corresponding stream of encoded video data. The systems and methods may include determining an operating state of the one or more input channels based on the flag bits. The operating state of an input channel may include an open state and a closed state of the input channel. The systems and methods may further include determining at least one of the one or more output channels to output the corresponding stream of decoded video data based on the input channels in the open state.