Invention Grant
- Patent Title: Layouts for interlevel crack prevention in fluxgate technology manufacturing
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Application No.: US16503660Application Date: 2019-07-05
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Publication No.: US12105161B2Publication Date: 2024-10-01
- Inventor: Sudtida Lavangkul , Sopa Chevacharoenkul
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Frank D. Cimino
- Main IPC: H10N50/01
- IPC: H10N50/01 ; G01R33/04 ; H10N50/80 ; H10N50/85

Abstract:
An integrated fluxgate device includes a substrate that includes a dielectric layer. A fluxgate core is located over the dielectric layer. Lower windings are disposed in a lower metal level between the fluxgate core and the dielectric layer, and upper windings are disposed in an upper metal level above the fluxgate core. A metal structure in the upper metal level or the lower metal level overlaps an end of the fluxgate core and is conductively isolated from the upper and lower windings.
Public/Granted literature
- US20190331742A1 LAYOUTS FOR INTERLEVEL CRACK PREVENTION IN FLUXGATE TECHNOLOGY MANUFACTURING Public/Granted day:2019-10-31
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