Invention Grant
- Patent Title: Apparatus and method for managing cache memory including cache lines with variable cache line configuration
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Application No.: US17969270Application Date: 2022-10-19
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Publication No.: US12105628B2Publication Date: 2024-10-01
- Inventor: Hyun-Mi Kim
- Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Applicant Address: KR Daejeon
- Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee Address: KR Daejeon
- Agency: KILE PARK REED & HOUTTEMAN PLLC
- Priority: KR 20210139512 2021.10.19 KR 20220071414 2022.06.13
- Main IPC: G06F12/0802
- IPC: G06F12/0802

Abstract:
Disclosed herein are an apparatus and method for managing cache memory. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program reads an s1-tag and an s2-tag of cache memory upon receiving an access request address for reading data in response to a request to access the cache memory, checks whether the access request address matches the value of the s1-tag and the value of the s2-tag, and reads the data from data memory when the access request address matches all of the value of the s1-tag and the value of the s2-tag.
Public/Granted literature
- US20230124538A1 APPARATUS AND METHOD FOR MANAGING CACHE MEMORY Public/Granted day:2023-04-20
Information query
IPC分类: