Invention Grant
- Patent Title: Independent gate length tunability for stacked transistors
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Application No.: US17411618Application Date: 2021-08-25
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Publication No.: US12107168B2Publication Date: 2024-10-01
- Inventor: Ruqiang Bao , Junli Wang , Dechao Guo
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Samuel Waldbaum
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L29/08 ; H01L29/10

Abstract:
A stacked FET structure having independently tuned gate lengths is provided to maximize the benefit of each FET within the stacked FET structure. Notably, a vertically stacked FET structure is provided in which a bottom FET has a different gate length than a top FET. In some embodiments, a dielectric spacer can be present laterally adjacent to the bottom FET and the top FET. In such an embodiment, the dielectric spacer can have a first portion that is located laterally adjacent to the bottom FET that has a different thickness than a second portion of the dielectric spacer that is located laterally adjacent the top FET.
Public/Granted literature
- US20230068484A1 INDEPENDENT GATE LENGTH TUNABILITY FOR STACKED TRANSISTORS Public/Granted day:2023-03-02
Information query
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