Invention Grant
- Patent Title: Manufacturing method of pillar-shaped semiconductor device
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Application No.: US17539431Application Date: 2021-12-01
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Publication No.: US12108585B2Publication Date: 2024-10-01
- Inventor: Fujio Masuoka , Nozomu Harada
- Applicant: Unisantis Electronics Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
- Current Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Crowell & Moring LLP
- Main IPC: H10B10/00
- IPC: H10B10/00 ; H01L29/66 ; H01L29/78

Abstract:
A gate TiN layer of adjacent Si pillars among Si pillars contacts at entire channel length in a vertical direction. SiO2 layers are formed, surrounding the Si pillars, and mask material layers on top thereof, and being spaced from each other. Then, a SiN layer is formed surrounding the SiO2 layers. Then, the mask material layers and the SiO2 layers are removed. Then, a P+ layer and N+ layers which upper surfaces are lower than an upper surface position of the SiN layer are formed surrounding each top of the Si pillars by selective epitaxial crystal growth method.
Public/Granted literature
- US20220093611A1 MANUFACTURING METHOD OF PILLAR-SHAPED SEMICONDUCTOR DEVICE Public/Granted day:2022-03-24
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