A semiconductor device, comprises a source, and a drain spaced apart from the source in a first direction. A channel layer is disposed on radially outer surfaces of the source and the drain in a second direction orthogonal to the first direction. A memory layer is disposed on a radially outer surface of the channel layer. A via is disposed at an axial end of the drain and is configured to electrically couple the drain to a global drain line. The via comprises a via base extending in a plane defined by the first direction and a second direction perpendicular to the first direction, and structured to contact the corresponding global drain line, and via sidewalls extending from outer peripheral edges of the base towards the drain. The via defines an internal cavity within which at least a portion of the axial end of the drain is disposed.