Invention Grant
- Patent Title: Methods for memory power management and memory devices and systems employing the same
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Application No.: US17991489Application Date: 2022-11-21
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Publication No.: US12112830B2Publication Date: 2024-10-08
- Inventor: Eric J. Stave , George E. Pax , Yogesh Sharma , Gregory A. King , Chan H. Yoo , Randon K. Richards , Timothy M. Hollis
- Applicant: Lodestar Licensing Group LLC
- Applicant Address: US IL Evanston
- Assignee: Lodestar Licensing Group LLC
- Current Assignee: Lodestar Licensing Group LLC
- Current Assignee Address: US IL Evanston
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/22 ; G11C16/10

Abstract:
Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.
Public/Granted literature
- US20230084286A1 METHODS FOR MEMORY POWER MANAGEMENT AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME Public/Granted day:2023-03-16
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