Invention Grant
- Patent Title: Integrated circuit including supervia and method of making
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Application No.: US18356354Application Date: 2023-07-21
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Publication No.: US12113014B2Publication Date: 2024-10-08
- Inventor: Kam-Tou Sio , Wei-Cheng Lin , Jiann-Tyng Tzeng
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- The original application number of the division: US16530770 2019.08.02
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/768 ; H01L23/528

Abstract:
An integrated circuit includes a substrate; and a first conductive line extending parallel to a top surface of the substrate. The first conductive line is a first distance from the substrate. The integrated circuit further includes a second conductive line extending parallel to the top surface of the substrate. The second conductive line is a second distance from the substrate. The integrated circuit further includes a third conductive line extending parallel to the top surface of the substrate. The third conductive line is a third distance from the substrate. The integrated circuit further includes a supervia directly connected to the first conductive line and the third conductive line, wherein a first angle between a sidewall of a lower portion of the supervia and the substrate is different from a second angle between a sidewall of an upper portion of the supervia and the substrate.
Public/Granted literature
- US20240021516A1 INTEGRATED CIRCUIT INCLUDING SUPERVIA AND METHOD OF MAKING Public/Granted day:2024-01-18
Information query
IPC分类: