Invention Grant
- Patent Title: Packed terminal transistors
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Application No.: US17651561Application Date: 2022-02-17
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Publication No.: US12113017B2Publication Date: 2024-10-08
- Inventor: Thomas Hua-Min Williams , Khaja Ahmad Shaik , Jeongah Park , Rinoj Thomas , Harini Siddaiah , Raj Kumar
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/522 ; H01L29/78

Abstract:
A die includes fins extending in a first direction, a gate formed over the fins, the gate extending in a second direction that is perpendicular to the first direction, a first source/drain contact layer formed over the fins and extending in the second direction, and a second source/drain contact layer formed over the fins and extending in the second direction, wherein the first source/drain contact layer and the second source/drain contact layer are on opposite sides of the gate. The die also includes a first source/drain metal layer electrically coupled to the first source/drain contact layer, and a second source/drain metal layer electrically coupled to the second source/drain contact layer, wherein the first source/drain metal layer and the second source/drain metal layer do not overlap one or more of the fins.
Public/Granted literature
- US20230260903A1 PACKED TERMINAL TRANSISTORS Public/Granted day:2023-08-17
Information query
IPC分类: