Invention Grant
- Patent Title: Chip package structure
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Application No.: US18344039Application Date: 2023-06-29
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Publication No.: US12113033B2Publication Date: 2024-10-08
- Inventor: Po-Chen Lai , Chin-Hua Wang , Ming-Chih Yew , Chia-Kuei Hsu , Li-Ling Liao , Po-Yao Lin , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L23/00 ; H01L25/00 ; H01L25/065

Abstract:
A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.
Public/Granted literature
- US20230343725A1 CHIP PACKAGE STRUCTURE Public/Granted day:2023-10-26
Information query
IPC分类: