Invention Grant
- Patent Title: Strain enhanced SiC power semiconductor device and method of manufacturing
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Application No.: US17633804Application Date: 2020-08-07
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Publication No.: US12113131B2Publication Date: 2024-10-08
- Inventor: Stephan Wirths , Lars Knoll
- Applicant: Hitachi Energy Ltd
- Applicant Address: CH Zürich
- Assignee: Hitachi Energy Ltd
- Current Assignee: Hitachi Energy Ltd
- Current Assignee Address: CH Zürich
- Agency: Slater Matsil, LLP
- Priority: EP 191095 2019.08.09
- International Application: PCT/EP2020/072295 2020.08.07
- International Announcement: WO2021/028353A 2021.02.18
- Date entered country: 2022-02-08
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/16 ; H01L29/51 ; H01L29/66 ; H01L29/739

Abstract:
A SiC transistor device includes a SiC semiconductor substrate, a SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, a source structure formed in the top surface of the SiC epitaxial layer, a source contact structure electrically coupled to the top surface of the source structure, and a gate structure that includes a gate dielectric, a metal gate, and a gate insulation. A first backside metal contact is formed on the bottom surface of the SiC semiconductor substrate, a stress inducing layer is formed on the first backside metal contact, and a second backside metal contact is formed on the stress inducing layer.
Public/Granted literature
- US20220302309A1 Strain Enhanced SiC Power Semiconductor Device and Method of Manufacturing Public/Granted day:2022-09-22
Information query
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